PhD · University at Buffalo

Aryan Pandey

I work on hardware-efficient machine learning — spiking and weightless neural networks, and the hardware that runs them at low power. PhD student in neuromorphic computing, with a focus on ML–hardware co-design and in-memory computing.

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About

I’m a PhD student in neuromorphic computing at the University at Buffalo, focused on hardware-efficient machine learning — spiking and weightless neural networks, ML–hardware co-design, and in-memory computing. The throughline of my work is making intelligence cheap to run: fewer MACs, lower power, architectures that fit the hardware.

Before the PhD I earned a B.S. in Computer Engineering at Buffalo and spent two years as a software engineer at Axon building large-scale cloud data infrastructure.

  • Education — Ph.D. Neuromorphic Computing, UB (2025–present) · B.S. Computer Engineering, UB
  • Interests — Hardware-efficient ML, ML–hardware co-design, in-memory computing, emerging compute architectures
  • Toolkit — PyTorch · CUDA · Triton · Norse · Verilog / Vivado · Cadence Virtuoso

Research

Recurrent Differentiable Weightless Networks

Added recurrence to weightless networks — a LUT-only family that replaces MACs with table lookups for far cheaper FPGA inference. 82.2% on Spiking Heidelberg Digits (vs. 67% feedforward) and 97.75% on N-MNIST; ran end-to-end on FPGA at 0.6 W via a PyTorch→Verilog export flow.

PyTorchVerilogFPGA

Hardware-Efficient RF Device Fingerprinting

An SNN that fingerprints radios straight from raw IQ samples using biologically-inspired spatiotemporal receptive fields with LIF/LI dynamics. Matched a CNN baseline on 30-device LoRa classification (99% validation), with metric-learning embeddings hitting 0.98 AUC for open-set rogue detection.

SNNNorsePyTorch

Multi-Objective NAS for SNNs

An LSTM-controller architecture search (REINFORCE) that trades off accuracy, spike sparsity, and temporal-coding quality (CV-ISI, Van Rossum distance). A gated reward avoids no-spike collapse; on Spiking Heidelberg Digits the controller converged decisively, beating random search under matched compute.

RLNASPyTorch

Experience

Research Software Engineering Fellow

Contributing to PsyNeuLink (open-source models of cognition). Building hierarchical Bayesian and neural-likelihood parameter estimation for simulator-based cognitive models, validated end-to-end on multi-subject drift-diffusion data.

Teaching Assistant — VLSI, Architecture, Security

Lead labs on CMOS standard-cell design and Cadence Virtuoso workflows (schematic → layout, parasitic extraction, DRC/LVS). Mentor teams through full-flow mixed-signal IC projects — DPLLs, TRNGs — from spec to tapeout.

Software Engineer

Built large-scale archival and ingestion on Azure (Temporal, Blob Storage) — cut cloud storage spend by $1.5M/month at 250 PB scale. Shipped Scala microservices on Kubernetes with 99.99%+ availability.

Education

Ph.D. in Neuromorphic Computing (Jan 2025 – present). B.S. in Computer Engineering, GPA 3.7, Dean’s List (2018 – 2022).

Photography

A few frames. More in the album →

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